Semiconductor devices are used in many electronic applications. Semiconductor devices are manufactured by depositing, patterning, and etching one or more conductive, insulating, and semiconductive layers on a semiconductor workpiece or wafer. Semiconductor devices may comprise analog or digital circuits, memory devices, logic circuits, peripheral support devices, or combinations thereof, formed on an integrated circuit (IC) die, as examples.
The trend in the semiconductor industry is towards the miniaturization or scaling of integrated circuits, in order to provide smaller ICs and improve performance, such as increased speed and decreased power consumption. While aluminum and aluminum alloys were most frequently used in the past for the material of conductive lines in integrated circuits, the trend is now towards the use of copper for a conductive line material because of its benefits of decreased resistance, higher conductivity and higher melting point, as examples. Another change in materials used for semiconductor device manufacturing is a trend away from the use of silicon dioxide for the insulating material between conductive lines and towards the use of low dielectric constant materials, which typically have a dielectric constant (k) less than the dielectric constant of silicon dioxide, which is about 4.0 to 4.5.
The change in the conductive line material and insulating materials of semiconductor devices has introduced new challenges in the manufacturing process. For example, copper oxidizes easily and has a tendency to diffuse into adjacent insulating materials, particularly when a low dielectric constant material or other porous insulator is used for an inter-level dielectric (ILD) material.
To prevent the diffusion of copper and other metals from migrating and poisoning the adjacent insulating layers, barrier layers or cap layers are often used in an attempt to prevent this diffusion. For example, SiNx, SiCxNyHz, and a bilayer of Ta/TaN having the same pattern as underlying conductive lines, have been used as etch stop layers and diffusion barriers, as described in “Comparison of Cu Electromigration Lifetime in Cu Interconnects Coated With Various Caps” in the Aug. 4, 2003 issue of Applied Physics Letters by Hu et al., which is incorporated herein by reference. Other proposed solutions are to provide a metal cap layer having the same pattern as underlying recessed conductive lines, wherein the metal cap layer comprises W, Ti, TiN, Ta, TaN, TiW, Al, CoWP, or CoP, as described in U.S. Pat. No. 6,709,874 issued to Ning on Mar. 23, 2004, which is incorporated herein by reference. In U.S. Pat. No. 6,680,500 issued to Low et al. on Jan. 20, 2004, also incorporated herein by reference, insulating cap layers comprised of SiN, and SiO2 are also proposed. The selective formation of CoWP over conductive lines is described in an article in the 2003 Symposium on VLSI Technology Digest of Technical Papers entitled “High Performance/reliability Cu Interconnect with Selective CoWP Cap,” by Ko et al., also incorporated herein by reference.
What is needed in the art is an improved method of preventing surface migration and diffusion of conductive line material into adjacent insulating materials.